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# What is the sampling operation of the A/D converter? (1)

Episode 14. Introducing details of sampling operation of SAR type and ZDS ADC.

This is a story that young A, who works in a fictional motor company deepens the knowledge of ADCs with a senior colleague K, and his boss, M, manager.

Senior K

Now, do you know more about the ADC?

Young A

Thanks to you, I understand much more!

Expert M Manager

Great.

Young A

However, I do not really understand the difference between a ZDS type and the SAR type ADC in the selection guide. The ZDS ADC is different from the ZDS-NS type, right? (Figure 1)

Senior K

From the user's point of view, the usage of the ZDS type and the SAR types are the same. Both are Nyquist ADCs sampling at one point.

Expert M Manager

Both the ZDS type and SAR type operate the same A/D conversion by adding a hold circuit to a ZDS-NS ADC for sampling at one point. (Figure 2)

Young A

Well then, does the oversampling effect of the ZDS-NS type disappear? That would be a waste.

Expert M Manager

On the other hand, you can make the acquisition time longer compared to the SAR type. For example, it is suitable for the input stage amplifier.

Young A

Excuse me, what is the acquisition time?

Expert M Manager

In order to understand the acquisition time, it is necessary to understand the ADC sampling operation.

Senior K

The analog input terminal of the ADC has a switched capacitor circuit configuration in which the capacitive element can be seen through the sampling switch. The analog input value is sampled by opening and closing this switch. (Figure 3)

Young A

I see. Acquisition time means that the sampling switch is connected to the analog input terminal and the input capacitance inside the ADC is visible from the outside, correct?

Senior K

Yes. Turning off this switch and disconnecting the input capacitance of the ADC from outside is called sampling. The analog voltage applied to the input capacitance at the moment of separation is A/D converted in the conversion phase and output as a digital code.

Young A

I didn't know ADC's had this kind of behavior. Did you need an input amplifier to drive this input capacitance?

... Hmm? The sampling timing of the ADC is controlled by the user, isn't it?

Senior K

You mean the timing of CSN pin falling or the CONVSTN pin falling. This is product dependent.

Young A

So, in Figure 3, how do you decide between conversion to acquisition boundaries? In other words, when does acquisition start?

Senior K

This is also product dependent.

Expert M Manager

It's an advantage of the ZDS type that acquisition starts fast, that is, you can take long acquisition times. (Figure 3)

Senior K

Driving the analog input of the ADC is the most difficult point to bring out the characteristics of the ADC written in the datasheet. The longer the acquisition time, the easier it is to bring out the characteristics.

Young A

Well ... the longer the acquisition time, the longer the time that the preamplifier can drive the ADC input capacitance, so the result is less load to the amplifier?

Expert M Manager

It seems that you have quite a good idea of an ADC's operation characteristics, great!

Young A

Why does the ZDS type usually take longer for acquisition?

Expert M Manager

For the SAR type configuration, it's necessary to keep the sampled analog voltage value in the input capacitance during the A/D conversion phase.

But, since the basic configuration of the ZDS ADC is a delta-sigma, an electric charge corresponds to the analog voltage signal stored in the input capacitance which can be transferred to the integration circuit.

Therefore, the input capacitance can be used at the middle of the A/D conversion phase. That's why you can start acquiring faster.

Senior K

In other words, the ZDS type can overlap the acquisition phase and the A/D conversion phase. So it's easy to make acquisition time longer than the SAR type.

Expert M Manager

Another point is that the input capacitance required to realize high resolution like 18 bits is small. The load on the amplifier is reduced and the kickback is also reduced.

Senior K

Kickback corresponds to the amount of charge on the previous input voltage stored in the input capacitance of the ADC that flows back to the outside of the ADC at the start timing of sampling. This is also troublesome.

Young A

... (there are still many things I do not know yet)